1. Field of the Invention
The present invention relates to a recording controller and a recording control method that carry out recording control of data with respect to a first cache and a second cache that are included in a processor.
2. Description of the Related Art
Recently, a cache is internally included in a processor and data that is recorded in a main memory is temporarily recorded in the cache, thus enhancing a process speed for a memory access (for example, see Japanese Patent Application Laid-open No. H11-134257). A structure of the existing processor is explained next.
FIG. 8 is a functional block diagram of the existing processor. As shown in FIG. 8, a processor 10 includes processor cores 20 and 30, a system controller (SC) 40, and a main memory 50. For the sake of convenience, only the processor cores 20 and 30 are shown in FIG. 8. However, the processor 10 includes a plurality of processor cores (the multiple processor cores are connected to the SC 40).
According to a data request from the processor cores 20 and 30, the SC 40 mainly retrieves data that is recorded or stored in the main memory 50 and distributes the retrieved data to the processor cores 20 and 30. The main memory 50 is a recording device that records therein the data (commands and data that is a calculation target) that is used by the processor cores 20 and 30.
The processor cores 20 and 30 retrieve the data that is recorded or stored in the main memory 50 and execute predetermined processes. Because the processor cores 20 and 30 include the same structural components, a structure of only the processor core 20 is explained. The processor core 20 includes a controller (command controller/calculating unit) 25a, a first cache 25b, and a second cache 25c. 
The controller 25a retrieves via the second cache 25c and the first cache 25b, the data that is recorded or stored in the main memory 50, interprets a command, and executes a predetermined process (a calculating process corresponding to the command etc.).
A structure of the existing second cache 25c is explained next. FIG. 9 is a functional block diagram of the existing second cache 25c. As shown in FIG. 9, the existing second cache 25c includes a move in (MI) port 60, arbitrating circuits 61 and 62, a pipeline 63, a cache tag 64, a move-in buffer 65, a move out (MO) port 66, an MO data buffer 67, and cache data unit 68.
Each process or operation of structural components of the second cache 25c is explained next. The MI port 60 receives (when data corresponding to a data request from the controller 25a is not recorded in the first cache 25b shown in FIG. 8) a data request (hereinafter, “MI request”) from the first cache 25b and outputs the MI request to the pipeline 63 via the arbitrating circuit 61.
Upon retrieving the MI request, the pipeline 63 determines, based on the cache tag 64, whether the data corresponding to the MI request exists in the second cache 25c. If the data corresponding to the MI request exists in the second cache 25c, the pipeline 63 searches the data from the cache data unit 68, and outputs the data to the first cache 25b. 
If the data corresponding to the MI request does not exist in the second cache 25c, the pipeline 63 outputs to the move-in buffer 65, data to the effect that the data corresponding to the MI request does not exist in the second cache 25c. Next, the move-in buffer 65 requests (outputs an SC request to the SC 40) the SC 40 for the data corresponding to the MI request. Next, upon retrieving the data corresponding to the MI request (hereinafter, “MI data”) from the SC 40, the move-in buffer 65 writes the MI data to an MI data buffer 65a and simultaneously transfers the MI data to the first cache 25b. 
Upon completing a preparation to record the MI data in the cache data unit 68, the move-in buffer 65 activates a new registration process and registers in the cache data unit 68, the MI data that is recorded in the MI data buffer 65a. 
However, upon retrieving the MI data and distributing the MI data to the controller 25a, the first cache 25b stores therein a calculation result by the controller 25a, thus storing therein the latest data compared to the second cache 25c. In the circumstances mentioned earlier, if the data of the first cache 25b is replaced, a write back to the second cache 25c occurs.
The MO port 66 retrieves the write back request (hereinafter, “MO request”) from the first cache 25b and outputs a request of a write back process (hereinafter, a write back request “WRBK”) to the pipeline 63 via the arbitrating circuit 61. Data, which is a write back target, (hereinafter, “MO data”) is registered in the MO data buffer 67.
Upon retrieving the request of the write back process, the pipeline 63 registers in the cache data unit 68 via the arbitrating circuit 62, the MO data that is recorded in the MO data buffer 67. Thus, the latest data (MO data) is recorded in the cache data unit 68.
However, in the conventional technology mentioned earlier, when writing back the data from the first cache 25b to the second cache 25c, if the new registration process by the move-in buffer 65 is not completed due to some reason, the latest data that is registered in the cache data unit 68 is lost.
FIG. 10 is a schematic diagram for explaining a drawback in the conventional technology. As shown in FIG. 10, the move-in buffer 65 retrieves the MI data from the SC 40 and registers the MI data in the MI data buffer 65a. Simultaneously, the MI data is transferred to the first cache 25b. The new registration process, which is carried out by the move-in buffer 65 that registers the MI data in the cache data unit 68, is likely to be delayed due to some reason (for example, if multiple data other than the MI data exist that need to be processed).
During a delay in the new registration process, if the latest data (MO data), which reflects the calculation result with respect to the MI data, is written back due to a replacing process of the first cache 25b, the MI data is recorded in the cache data unit 68 on the second cache 25c after the MO data is recorded in the cache data unit 68. In other words, the latest data is overwritten by obsolete data.